The present invention relates in general to programmable logic devices (PLDs), and in particular to dynamic configurable elements for PLDs.
Programmable logic devices are circuits that include a large number of logic gates whose logic function and interconnection can be programmed via programmable elements to form a desired logic function. Programmability is achieved using any one of a variety of programmable technologies, such as fusible links, erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM. A fuse element is typically a small value resistor as fabricated which is selectively transformed into an open circuit upon programming. EPROM technology uses a transistor that has low turn on voltage upon fabrication, and is selectively transformed into an open circuit by raising the turn on voltage higher than the power supply during programming. EEPROM technology produces a high turn on voltage transistor after bulk erasure, and selectively transforms the transistor into a depletion mode device by electrically reducing the turn on voltage to below zero volts.
All of the above-mentioned programmable technologies fall in the non-volatile category. That is, when the power is removed from the circuit momentarily, these programmable elements retain the programmed information. It is therefore only necessary to load the programming information into the part once. For the fuse based PLD, it is impossible to reverse the programming (or patterning) step. For the EPROM based PLD about half an hour of exposure to ultra violet radiation is required to deprogram the device. For the EEPROM and flash EEPROM based PLD, the programmable element may be reset to its initial state using less than a few minutes of electrical stress.
Another type of programmable element used in PLDs is the static random access memory (SRAM) cell. An SRAM cell operates as a bistable latch. FIG. 1 shows an SRAM cell 100 having an access transistor 102 and a pair of back-to-back connected inverters 104 that acts as a latch. The cell 100 drives the gate terminal of a pass transistor 106 that forms part of the programmable logic gate. The SRAM cell does not retain its contents when power is removed. For this reason an external source of programming (or configuration) data must be provided along with an SRAM based PLD for reconfiguring the PLD in case of a momentary power failure. Once the PLD is reconfigured upon power up, however, the source of configuration data is idle and serves no purpose during the operation of the PLD.
There are advantages and disadvantages associated with both the volatile and the non-volatile programmable technologies. The programmable element in the non-volatile technologies tend to be smaller in size which enhance the logic density of a PLD. However, PLDs using any one of the non-volatile programmable technologies require special fabrication steps which increase the cost of manufacture and reduce the number of qualified sources of manufactured silicon wafer. The SRAM based PLDs on the other hand may be fabricated on, for example, a standard complementary metal-oxide-semiconductor (CMOS) process or a process tuned for CMOS logic and SRAM circuits. The cost of manufactured wafers is thus lower for the SRAM based PLDs with many more qualified sources of manufactured wafers. As can be seen by the required circuitry in FIG. 1, the SRAM cell however is considerably larger than its non-volatile counterparts. With today's technologies, a typical SRAM cell may be twice as large as an EEPROM cell and ten times the size of an EPROM or flash EEPROM cell.
An approach for a PLD design that retains the low cost and manufacturability of SRAM based PLDs while reducing the size of the programmable element is offered by Wahlstrom in U.S. Pat. No. 5,317,212. Wahlstrom teaches using a dynamic random access memory (DRAM) cell as the programmable element in a PLD instead of an SRAM cell. The DRAM cell can be fabricated using standard CMOS technology, and typically includes a small storage capacitor coupled to a single small access transistor which results in a much smaller cell.
Because DRAM cells dynamically store the configuration data on leaky storage capacitors, the cells require periodic refreshing. A typical DRAM refresh cycle includes the steps of addressing the cells, sensing their contents (i.e. logic high or logic low), and writing the information back in the cells. Thus, to refresh DRAM cells, the circuit must perform a read operation before writing back. This requires additional circuitry, such as sense amplifiers. Also, because a read operation disturbs the amount of charge stored on the cell capacitor, the operation of the PLD must be synchronized to avoid reading of the cells during refresh. This requires more circuitry and tends to limit the operating speed of the circuit. Wahlstrom offers various embodiments to allow the PLD to rely on the DRAM cell voltage even during a refresh cycle. However, the various embodiments of the proposed DRAM cell either require larger storage capacitors or additional circuit elements that result in an overall larger programmable cell. There is therefore room for further improvements in the design of smaller and more cost effective programmable elements for PLDs.